{"slug":"electrical-engineer","title":"Electrical Engineer","metadata":{"title":"Electrical Engineer","slug":"electrical-engineer","aliases":["Electronics Engineer","Power Engineer","EE"],"category":"Engineering","tags":["circuits","electronics","power","signal-integrity","emc"],"difficulty":"advanced","summary":"Designs electrical and electronic systems that meet voltage, current, timing, and signal goals with margin while surviving heat, tolerance, and noise.","contributors":["soul-atlas"],"last_reviewed":null,"provenance":"ai-generated","created":"2026-06-26","updated":"2026-06-26","related":[{"slug":"mechanical-engineer","type":"collaboration","note":"owns the enclosure and the thermal path for electronics"},{"slug":"embedded-systems-engineer","type":"adjacent","note":"writes firmware that runs the silicon; shares hardware/software boundary"},{"slug":"robotics-engineer","type":"related","note":"combines power electronics, sensing, and control"},{"slug":"network-engineer","type":"adjacent","note":"builds on the physical layer electrical engineers define"},{"slug":"electrician","type":"adjacent","note":"installs and maintains power systems at building scale"}],"specializations":["Power Systems Engineer","Analog Design Engineer","RF Engineer","Power Electronics Engineer"],"country_variants":[],"sources":[{"title":"The Art of Electronics","kind":"book"},{"title":"Noise Reduction Techniques in Electronic Systems","kind":"book"}],"status":"draft","reviewers":[]},"sections":[{"heading":"Purpose","id":"purpose","markdown":"Electrical engineering exists to move and shape electrical energy and\ninformation — power that lights cities and signals that carry meaning — through\ncircuits, fields, and devices governed by physics most people never see. An\nelectrical engineer's reason for being is to design circuits and systems that\ndeliver the right voltage, current, and signal at the right time, that don't burn\nup, oscillate, radiate, or brown out, and that keep working across temperature,\ncomponent tolerance, and the noise of the real world. The discipline spans from\nthe femtoamps of a sensor front end to the megawatts of a substation, unified by\nthe same equations and the same enemy: the parasitic effect you didn't model.","html":"<h2 id=\"purpose\">Purpose</h2>\n<p>Electrical engineering exists to move and shape electrical energy and\ninformation — power that lights cities and signals that carry meaning — through\ncircuits, fields, and devices governed by physics most people never see. An\nelectrical engineer&#39;s reason for being is to design circuits and systems that\ndeliver the right voltage, current, and signal at the right time, that don&#39;t burn\nup, oscillate, radiate, or brown out, and that keep working across temperature,\ncomponent tolerance, and the noise of the real world. The discipline spans from\nthe femtoamps of a sensor front end to the megawatts of a substation, unified by\nthe same equations and the same enemy: the parasitic effect you didn&#39;t model.</p>\n","wordCount":112},{"heading":"Core Mission","id":"core-mission","markdown":"Design electrical and electronic systems that meet their voltage, current,\ntiming, and signal-integrity requirements with margin, dissipate their heat,\nsurvive component tolerance and noise, and comply with the safety and EMC\nstandards that make them legal to sell.","html":"<h2 id=\"core-mission\">Core Mission</h2>\n<p>Design electrical and electronic systems that meet their voltage, current,\ntiming, and signal-integrity requirements with margin, dissipate their heat,\nsurvive component tolerance and noise, and comply with the safety and EMC\nstandards that make them legal to sell.</p>\n","wordCount":39},{"heading":"Primary Responsibilities","id":"primary-responsibilities","markdown":"The visible output is schematics and PCB layouts, but the work is taming physics\nthat hides in the layout. An electrical engineer designs and analyzes circuits;\nbudgets power and manages thermal dissipation; ensures signal integrity at speed;\ndesigns for electromagnetic compatibility so the product neither emits nor\nsuccumbs to interference; selects components against derating, tolerance, and\navailability; lays out boards where the copper and the return path are part of\nthe circuit; designs grounding and shielding; brings up and debugs hardware with\nan oscilloscope; and certifies the product against safety (UL/IEC) and emissions\n(FCC/CISPR) standards. Underneath is the discipline of margin — deratings, worst-\ncase analysis, and the tolerance stack that decides whether the design works on\nevery unit or just the prototype.","html":"<h2 id=\"primary-responsibilities\">Primary Responsibilities</h2>\n<p>The visible output is schematics and PCB layouts, but the work is taming physics\nthat hides in the layout. An electrical engineer designs and analyzes circuits;\nbudgets power and manages thermal dissipation; ensures signal integrity at speed;\ndesigns for electromagnetic compatibility so the product neither emits nor\nsuccumbs to interference; selects components against derating, tolerance, and\navailability; lays out boards where the copper and the return path are part of\nthe circuit; designs grounding and shielding; brings up and debugs hardware with\nan oscilloscope; and certifies the product against safety (UL/IEC) and emissions\n(FCC/CISPR) standards. Underneath is the discipline of margin — deratings, worst-\ncase analysis, and the tolerance stack that decides whether the design works on\nevery unit or just the prototype.</p>\n","wordCount":124},{"heading":"Guiding Principles","id":"guiding-principles","markdown":"- **The current always returns.** Every signal has a return path; if you don't\n  control where it flows, it flows through your ground and becomes noise. Layout\n  is circuit design.\n- **Derate everything.** Run components below their rated voltage, current,\n  power, and temperature. A capacitor at its rated voltage is a capacitor near\n  failure.\n- **Worst-case, not nominal.** Design so the circuit works when every tolerance,\n  temperature, and supply rail lands at its worst corner simultaneously.\n- **Manage the heat or it manages you.** Every watt dissipated has to leave; the\n  junction temperature, not the datasheet, decides device life.\n- **EMC is designed in, not added on.** You cannot filter your way out of a bad\n  layout at the certification lab.\n- **Measure before you theorize.** The oscilloscope and the spectrum analyzer\n  see the parasitics your schematic doesn't.\n- **Respect the voltage that can kill.** Mains and high-voltage design is a\n  safety discipline first and a performance discipline second.","html":"<h2 id=\"guiding-principles\">Guiding Principles</h2>\n<ul>\n<li><strong>The current always returns.</strong> Every signal has a return path; if you don&#39;t\ncontrol where it flows, it flows through your ground and becomes noise. Layout\nis circuit design.</li>\n<li><strong>Derate everything.</strong> Run components below their rated voltage, current,\npower, and temperature. A capacitor at its rated voltage is a capacitor near\nfailure.</li>\n<li><strong>Worst-case, not nominal.</strong> Design so the circuit works when every tolerance,\ntemperature, and supply rail lands at its worst corner simultaneously.</li>\n<li><strong>Manage the heat or it manages you.</strong> Every watt dissipated has to leave; the\njunction temperature, not the datasheet, decides device life.</li>\n<li><strong>EMC is designed in, not added on.</strong> You cannot filter your way out of a bad\nlayout at the certification lab.</li>\n<li><strong>Measure before you theorize.</strong> The oscilloscope and the spectrum analyzer\nsee the parasitics your schematic doesn&#39;t.</li>\n<li><strong>Respect the voltage that can kill.</strong> Mains and high-voltage design is a\nsafety discipline first and a performance discipline second.</li>\n</ul>\n","wordCount":154},{"heading":"Mental Models","id":"mental-models","markdown":"- **Kirchhoff and the return path.** KCL and KVL are bookkeeping; the deeper\n  model is that current flows in loops and the return path's geometry sets\n  inductance, noise, and EMI. Find the loop.\n- **Impedance everywhere.** At DC it's resistance; at frequency, everything has\n  reactance — the trace is an inductor, the gap is a capacitor — and matched\n  impedance is what keeps fast signals from reflecting.\n- **Derating and the bathtub curve.** Components fail early (infant mortality),\n  randomly (useful life), and by wear-out; derating and burn-in push operation\n  into the flat bottom of the curve.\n- **Worst-case / Monte Carlo tolerance.** Component values are distributions;\n  analyze the design across the tolerance corners and over temperature, not at\n  the typical value.\n- **The decoupling and the loop area.** A fast device needs local charge; the\n  decoupling cap and its loop to the device are what supply transient current\n  without dipping the rail.\n- **Thermal resistance network.** Junction-to-case-to-heatsink-to-ambient is a\n  chain of thermal resistances; the junction temperature is the voltage across\n  it driven by dissipated power.\n- **Signal-to-noise and the noise floor.** Every measurement sits above a noise\n  floor; gain, bandwidth, and shielding decide how small a signal you can\n  recover.","html":"<h2 id=\"mental-models\">Mental Models</h2>\n<ul>\n<li><strong>Kirchhoff and the return path.</strong> KCL and KVL are bookkeeping; the deeper\nmodel is that current flows in loops and the return path&#39;s geometry sets\ninductance, noise, and EMI. Find the loop.</li>\n<li><strong>Impedance everywhere.</strong> At DC it&#39;s resistance; at frequency, everything has\nreactance — the trace is an inductor, the gap is a capacitor — and matched\nimpedance is what keeps fast signals from reflecting.</li>\n<li><strong>Derating and the bathtub curve.</strong> Components fail early (infant mortality),\nrandomly (useful life), and by wear-out; derating and burn-in push operation\ninto the flat bottom of the curve.</li>\n<li><strong>Worst-case / Monte Carlo tolerance.</strong> Component values are distributions;\nanalyze the design across the tolerance corners and over temperature, not at\nthe typical value.</li>\n<li><strong>The decoupling and the loop area.</strong> A fast device needs local charge; the\ndecoupling cap and its loop to the device are what supply transient current\nwithout dipping the rail.</li>\n<li><strong>Thermal resistance network.</strong> Junction-to-case-to-heatsink-to-ambient is a\nchain of thermal resistances; the junction temperature is the voltage across\nit driven by dissipated power.</li>\n<li><strong>Signal-to-noise and the noise floor.</strong> Every measurement sits above a noise\nfloor; gain, bandwidth, and shielding decide how small a signal you can\nrecover.</li>\n</ul>\n","wordCount":201},{"heading":"First Principles","id":"first-principles","markdown":"- Charge is conserved and current flows in complete loops, always.\n- Every conductor has resistance, inductance, and capacitance whether you drew\n  them or not.\n- A component's life is governed by its temperature and voltage stress, not its\n  part number.\n- Noise is not optional; you design the signal to live above it.\n- The voltage on the schematic is nominal; the voltage in the field varies.","html":"<h2 id=\"first-principles\">First Principles</h2>\n<ul>\n<li>Charge is conserved and current flows in complete loops, always.</li>\n<li>Every conductor has resistance, inductance, and capacitance whether you drew\nthem or not.</li>\n<li>A component&#39;s life is governed by its temperature and voltage stress, not its\npart number.</li>\n<li>Noise is not optional; you design the signal to live above it.</li>\n<li>The voltage on the schematic is nominal; the voltage in the field varies.</li>\n</ul>\n","wordCount":63},{"heading":"Questions Experts Constantly Ask","id":"questions-experts-constantly-ask","markdown":"- Where does the return current flow, and what loop area does it enclose?\n- What's the worst-case corner — tolerance, temperature, supply — and does it\n  still work?\n- Have I derated this part, and what's its junction temperature at full load?\n- What's the impedance at the frequencies that matter?\n- Where's the decoupling, and how big is its loop?\n- Will this pass EMC, and where will it radiate or pick up?\n- What happens when the supply browns out or a load shorts?\n- Is anything here at a voltage that can hurt someone?","html":"<h2 id=\"questions-experts-constantly-ask\">Questions Experts Constantly Ask</h2>\n<ul>\n<li>Where does the return current flow, and what loop area does it enclose?</li>\n<li>What&#39;s the worst-case corner — tolerance, temperature, supply — and does it\nstill work?</li>\n<li>Have I derated this part, and what&#39;s its junction temperature at full load?</li>\n<li>What&#39;s the impedance at the frequencies that matter?</li>\n<li>Where&#39;s the decoupling, and how big is its loop?</li>\n<li>Will this pass EMC, and where will it radiate or pick up?</li>\n<li>What happens when the supply browns out or a load shorts?</li>\n<li>Is anything here at a voltage that can hurt someone?</li>\n</ul>\n","wordCount":89},{"heading":"Decision Frameworks","id":"decision-frameworks","markdown":"- **Worst-case analysis (WCA).** For anything that must work on every unit,\n  compute the output across all tolerance and temperature corners; if the worst\n  corner fails, the design is wrong even if the prototype works.\n- **Derating policy.** Apply standard deratings (e.g., 50% of rated voltage on\n  electrolytics, 80% on current, junction temp margin) per a documented standard\n  like MIL-HDBK or the company derating spec.\n- **Linear vs. switching regulator.** Choose by efficiency, heat, and noise — a\n  linear regulator is quiet and dissipative, a switcher is efficient and noisy;\n  the load and thermal budget decide.\n- **Integration vs. discrete.** Buy the IC that integrates the function unless\n  the requirement is outside any part's spec, then design discrete and own the\n  complexity.\n- **EMC mitigation order.** Fix at the source (layout, edge rates), then the path\n  (shielding, grounding), then the receptor (filtering) — cheapest and most\n  effective at the source.","html":"<h2 id=\"decision-frameworks\">Decision Frameworks</h2>\n<ul>\n<li><strong>Worst-case analysis (WCA).</strong> For anything that must work on every unit,\ncompute the output across all tolerance and temperature corners; if the worst\ncorner fails, the design is wrong even if the prototype works.</li>\n<li><strong>Derating policy.</strong> Apply standard deratings (e.g., 50% of rated voltage on\nelectrolytics, 80% on current, junction temp margin) per a documented standard\nlike MIL-HDBK or the company derating spec.</li>\n<li><strong>Linear vs. switching regulator.</strong> Choose by efficiency, heat, and noise — a\nlinear regulator is quiet and dissipative, a switcher is efficient and noisy;\nthe load and thermal budget decide.</li>\n<li><strong>Integration vs. discrete.</strong> Buy the IC that integrates the function unless\nthe requirement is outside any part&#39;s spec, then design discrete and own the\ncomplexity.</li>\n<li><strong>EMC mitigation order.</strong> Fix at the source (layout, edge rates), then the path\n(shielding, grounding), then the receptor (filtering) — cheapest and most\neffective at the source.</li>\n</ul>\n","wordCount":146},{"heading":"Workflow","id":"workflow","markdown":"1. **Specify.** Define voltages, currents, signals, timing, environment, and the\n   safety/EMC standards the product must meet.\n2. **Architect.** Block the system, budget power and the noise/thermal envelope,\n   pick the topology before drawing a transistor.\n3. **Schematic.** Design the circuit, select and derate components, and run\n   worst-case analysis on the critical nodes.\n4. **Layout.** Place and route with the return path, loop area, decoupling, and\n   thermal in mind; layout is where the design succeeds or fails.\n5. **Simulate.** SPICE the critical analog, run signal-integrity and thermal\n   models, validated against a hand estimate.\n6. **Bring-up.** Power the board on a current-limited supply, probe rails and\n   signals, and find where reality and schematic diverge.\n7. **Qualify.** EMC pre-compliance, thermal soak, and worst-case unit testing\n   before formal certification.\n8. **Release and support.** Production test, yield analysis, and field-failure\n   diagnosis.","html":"<h2 id=\"workflow\">Workflow</h2>\n<ol>\n<li><strong>Specify.</strong> Define voltages, currents, signals, timing, environment, and the\nsafety/EMC standards the product must meet.</li>\n<li><strong>Architect.</strong> Block the system, budget power and the noise/thermal envelope,\npick the topology before drawing a transistor.</li>\n<li><strong>Schematic.</strong> Design the circuit, select and derate components, and run\nworst-case analysis on the critical nodes.</li>\n<li><strong>Layout.</strong> Place and route with the return path, loop area, decoupling, and\nthermal in mind; layout is where the design succeeds or fails.</li>\n<li><strong>Simulate.</strong> SPICE the critical analog, run signal-integrity and thermal\nmodels, validated against a hand estimate.</li>\n<li><strong>Bring-up.</strong> Power the board on a current-limited supply, probe rails and\nsignals, and find where reality and schematic diverge.</li>\n<li><strong>Qualify.</strong> EMC pre-compliance, thermal soak, and worst-case unit testing\nbefore formal certification.</li>\n<li><strong>Release and support.</strong> Production test, yield analysis, and field-failure\ndiagnosis.</li>\n</ol>\n","wordCount":144},{"heading":"Common Tradeoffs","id":"common-tradeoffs","markdown":"- **Efficiency vs. noise.** Switching converters are efficient and noisy; linear\n  regulators are clean and hot. The sensitive analog rail and the thermal budget\n  decide.\n- **Performance vs. EMC.** Faster edges mean faster logic and more emissions;\n  slow the edges you don't need to be fast.\n- **Cost vs. margin.** A cheaper part at tighter derating is a warranty cost\n  deferred; the BOM line is visible, the field failure is not.\n- **Integration vs. flexibility.** A highly integrated IC is small and cheap but\n  fixed; discrete design is flexible and larger.\n- **Board area vs. layer count.** More layers ease routing and improve signal\n  integrity but raise cost; fewer layers force harder layout.\n- **Precision vs. power.** Lower noise and higher accuracy usually cost current\n  and heat.","html":"<h2 id=\"common-tradeoffs\">Common Tradeoffs</h2>\n<ul>\n<li><strong>Efficiency vs. noise.</strong> Switching converters are efficient and noisy; linear\nregulators are clean and hot. The sensitive analog rail and the thermal budget\ndecide.</li>\n<li><strong>Performance vs. EMC.</strong> Faster edges mean faster logic and more emissions;\nslow the edges you don&#39;t need to be fast.</li>\n<li><strong>Cost vs. margin.</strong> A cheaper part at tighter derating is a warranty cost\ndeferred; the BOM line is visible, the field failure is not.</li>\n<li><strong>Integration vs. flexibility.</strong> A highly integrated IC is small and cheap but\nfixed; discrete design is flexible and larger.</li>\n<li><strong>Board area vs. layer count.</strong> More layers ease routing and improve signal\nintegrity but raise cost; fewer layers force harder layout.</li>\n<li><strong>Precision vs. power.</strong> Lower noise and higher accuracy usually cost current\nand heat.</li>\n</ul>\n","wordCount":121},{"heading":"Rules of Thumb","id":"rules-of-thumb","markdown":"- Put a decoupling cap at every power pin and keep its loop tiny.\n- A solid, unbroken ground plane fixes more EMI than any filter.\n- If it oscillates, suspect a feedback loop or a missing decoupling cap.\n- Derate electrolytics to half their rated voltage; they age fastest.\n- Slow the edge rate to the slowest the timing allows — emissions drop fast.\n- The junction temperature, not the case, sets the part's life.\n- Probe the rail before you blame the firmware.","html":"<h2 id=\"rules-of-thumb\">Rules of Thumb</h2>\n<ul>\n<li>Put a decoupling cap at every power pin and keep its loop tiny.</li>\n<li>A solid, unbroken ground plane fixes more EMI than any filter.</li>\n<li>If it oscillates, suspect a feedback loop or a missing decoupling cap.</li>\n<li>Derate electrolytics to half their rated voltage; they age fastest.</li>\n<li>Slow the edge rate to the slowest the timing allows — emissions drop fast.</li>\n<li>The junction temperature, not the case, sets the part&#39;s life.</li>\n<li>Probe the rail before you blame the firmware.</li>\n</ul>\n","wordCount":77},{"heading":"Failure Modes","id":"failure-modes","markdown":"- **Ignoring the return path,** so a clean schematic radiates and picks up noise\n  on the bench.\n- **Designing at nominal,** so the prototype works and 1 in 50 production units\n  doesn't.\n- **No derating,** so parts run hot and the field-failure rate climbs after\n  warranty.\n- **Treating EMC as a lab problem,** discovered too late to fix without a\n  respin.\n- **Underestimating thermal,** so the device throttles or fails at full load in\n  a closed enclosure.\n- **Trusting the datasheet typical** instead of the min/max over temperature.\n- **Probing with a long ground lead,** then chasing the noise the probe injected.","html":"<h2 id=\"failure-modes\">Failure Modes</h2>\n<ul>\n<li><strong>Ignoring the return path,</strong> so a clean schematic radiates and picks up noise\non the bench.</li>\n<li><strong>Designing at nominal,</strong> so the prototype works and 1 in 50 production units\ndoesn&#39;t.</li>\n<li><strong>No derating,</strong> so parts run hot and the field-failure rate climbs after\nwarranty.</li>\n<li><strong>Treating EMC as a lab problem,</strong> discovered too late to fix without a\nrespin.</li>\n<li><strong>Underestimating thermal,</strong> so the device throttles or fails at full load in\na closed enclosure.</li>\n<li><strong>Trusting the datasheet typical</strong> instead of the min/max over temperature.</li>\n<li><strong>Probing with a long ground lead,</strong> then chasing the noise the probe injected.</li>\n</ul>\n","wordCount":97},{"heading":"Anti-patterns","id":"anti-patterns","markdown":"- **Star-ground cargo cult** — applying a grounding rule without the layout it\n  was meant for.\n- **Filter-it-later** — bolting on ferrites and caps to fix a layout that\n  radiates.\n- **Datasheet-typical design** — sizing to typical values, not min/max corners.\n- **Magic decoupling** — scattering 0.1 µF caps without thinking about loop area\n  or resonance.\n- **Schematic-only thinking** — treating layout as a drafting task, not circuit\n  design.\n- **Hero debugging** — swapping parts until it works without understanding the\n  fault.","html":"<h2 id=\"anti-patterns\">Anti-patterns</h2>\n<ul>\n<li><strong>Star-ground cargo cult</strong> — applying a grounding rule without the layout it\nwas meant for.</li>\n<li><strong>Filter-it-later</strong> — bolting on ferrites and caps to fix a layout that\nradiates.</li>\n<li><strong>Datasheet-typical design</strong> — sizing to typical values, not min/max corners.</li>\n<li><strong>Magic decoupling</strong> — scattering 0.1 µF caps without thinking about loop area\nor resonance.</li>\n<li><strong>Schematic-only thinking</strong> — treating layout as a drafting task, not circuit\ndesign.</li>\n<li><strong>Hero debugging</strong> — swapping parts until it works without understanding the\nfault.</li>\n</ul>\n","wordCount":77},{"heading":"Vocabulary","id":"vocabulary","markdown":"- **Derating** — operating a component below its rated stress for reliability.\n- **Return path** — the route current takes back to its source; sets loop area\n  and noise.\n- **Impedance** — opposition to AC current; resistance plus reactance.\n- **Decoupling capacitor** — local charge reservoir that supplies transient\n  current to a device.\n- **EMC / EMI** — electromagnetic compatibility; emissions and immunity.\n- **Signal integrity** — preserving a signal's shape and timing at speed.\n- **Worst-case analysis** — verifying function across all tolerance and\n  temperature corners.\n- **Junction temperature** — the temperature of a semiconductor die; sets life.\n- **Slew rate / edge rate** — how fast a signal transitions; drives emissions.\n- **Ground bounce** — supply/ground shifting under switching current.","html":"<h2 id=\"vocabulary\">Vocabulary</h2>\n<ul>\n<li><strong>Derating</strong> — operating a component below its rated stress for reliability.</li>\n<li><strong>Return path</strong> — the route current takes back to its source; sets loop area\nand noise.</li>\n<li><strong>Impedance</strong> — opposition to AC current; resistance plus reactance.</li>\n<li><strong>Decoupling capacitor</strong> — local charge reservoir that supplies transient\ncurrent to a device.</li>\n<li><strong>EMC / EMI</strong> — electromagnetic compatibility; emissions and immunity.</li>\n<li><strong>Signal integrity</strong> — preserving a signal&#39;s shape and timing at speed.</li>\n<li><strong>Worst-case analysis</strong> — verifying function across all tolerance and\ntemperature corners.</li>\n<li><strong>Junction temperature</strong> — the temperature of a semiconductor die; sets life.</li>\n<li><strong>Slew rate / edge rate</strong> — how fast a signal transitions; drives emissions.</li>\n<li><strong>Ground bounce</strong> — supply/ground shifting under switching current.</li>\n</ul>\n","wordCount":102},{"heading":"Tools","id":"tools","markdown":"- **SPICE** (LTspice, PSpice) — analog circuit simulation.\n- **EDA / PCB tools** (Altium, KiCad, Cadence Allegro) — schematic capture and\n  layout.\n- **Oscilloscope and spectrum analyzer** — to see the parasitics the schematic\n  hides.\n- **Bench supply with current limit, DMM, function generator** — the daily\n  bring-up kit.\n- **Thermal camera and thermocouples** — to find the hot junction.\n- **EMC pre-compliance gear** (near-field probes, LISN) — to fix emissions before\n  the certification lab.\n- **Standards** (IEC 61010/60950, UL, FCC Part 15, CISPR) — the legal targets.","html":"<h2 id=\"tools\">Tools</h2>\n<ul>\n<li><strong>SPICE</strong> (LTspice, PSpice) — analog circuit simulation.</li>\n<li><strong>EDA / PCB tools</strong> (Altium, KiCad, Cadence Allegro) — schematic capture and\nlayout.</li>\n<li><strong>Oscilloscope and spectrum analyzer</strong> — to see the parasitics the schematic\nhides.</li>\n<li><strong>Bench supply with current limit, DMM, function generator</strong> — the daily\nbring-up kit.</li>\n<li><strong>Thermal camera and thermocouples</strong> — to find the hot junction.</li>\n<li><strong>EMC pre-compliance gear</strong> (near-field probes, LISN) — to fix emissions before\nthe certification lab.</li>\n<li><strong>Standards</strong> (IEC 61010/60950, UL, FCC Part 15, CISPR) — the legal targets.</li>\n</ul>\n","wordCount":77},{"heading":"Collaboration","id":"collaboration","markdown":"Electrical work shares a physical box and a schedule with several disciplines.\nEngineers work with mechanical engineers (who own the enclosure and the thermal\npath), firmware/software engineers (who run the silicon), PCB layout designers,\ntest engineers, and contract manufacturers. The friction lives at the boundaries\n— where the connector won't fit the housing, where the heat the EE generates\nexceeds the mechanical cooling, where firmware blames hardware and hardware\nblames firmware for a glitch on the scope. Good engineers settle the\nhardware/software fault by putting the probe on the pin, negotiate the thermal\nbudget with mechanical early, and hand the layout designer the constraints\n(impedance, loop, keep-out) rather than the routing.","html":"<h2 id=\"collaboration\">Collaboration</h2>\n<p>Electrical work shares a physical box and a schedule with several disciplines.\nEngineers work with mechanical engineers (who own the enclosure and the thermal\npath), firmware/software engineers (who run the silicon), PCB layout designers,\ntest engineers, and contract manufacturers. The friction lives at the boundaries\n— where the connector won&#39;t fit the housing, where the heat the EE generates\nexceeds the mechanical cooling, where firmware blames hardware and hardware\nblames firmware for a glitch on the scope. Good engineers settle the\nhardware/software fault by putting the probe on the pin, negotiate the thermal\nbudget with mechanical early, and hand the layout designer the constraints\n(impedance, loop, keep-out) rather than the routing.</p>\n","wordCount":113},{"heading":"Ethics","id":"ethics","markdown":"Electrical engineers design things that can electrocute, overheat, catch fire,\nand interfere with other people's equipment, which makes safety standards a moral\nfloor, not a paperwork ceiling. The duties: design isolation, fusing, and\nfail-safes into anything connected to mains or carrying dangerous energy; never\nship a product that hasn't actually met its safety and EMC standards even when\nthe schedule is tight; be honest about reliability and the deratings you skipped;\nand recognize that an emissions failure is your product degrading someone else's.\nThe recurring gray zone is the cost-down that removes a fuse, a clearance, or a\nmargin that \"probably isn't needed\" — defensible per unit, and exactly the\ndecision that puts an under-protected product in someone's hands.","html":"<h2 id=\"ethics\">Ethics</h2>\n<p>Electrical engineers design things that can electrocute, overheat, catch fire,\nand interfere with other people&#39;s equipment, which makes safety standards a moral\nfloor, not a paperwork ceiling. The duties: design isolation, fusing, and\nfail-safes into anything connected to mains or carrying dangerous energy; never\nship a product that hasn&#39;t actually met its safety and EMC standards even when\nthe schedule is tight; be honest about reliability and the deratings you skipped;\nand recognize that an emissions failure is your product degrading someone else&#39;s.\nThe recurring gray zone is the cost-down that removes a fuse, a clearance, or a\nmargin that &quot;probably isn&#39;t needed&quot; — defensible per unit, and exactly the\ndecision that puts an under-protected product in someone&#39;s hands.</p>\n","wordCount":121},{"heading":"Scenarios","id":"scenarios","markdown":"**A board that fails EMC at the certification lab.** A product passes every\nfunctional test and fails radiated emissions at a clock harmonic. The expert does\nnot reach for ferrites first. They open the layout, find the high-speed clock\ntrace routed over a split in the ground plane, and realize the return current was\nforced into a large loop that became an antenna. The fix is in the copper: route\nthe clock over solid ground, shorten the return loop, and slow the edge rate to\nthe slowest the timing allows. The filter would have masked a symptom; the layout\nfixed the cause.\n\n**A regulator that overheats in the enclosure.** A linear regulator drops a high\ninput voltage to a low rail at significant current and runs fine on the open\nbench, then thermal-shuts-down inside the sealed product. The engineer computes\nthe dissipation (voltage drop times current) and the junction temperature through\nthe thermal-resistance chain, sees there's no path to ambient in the closed box,\nand switches to a switching regulator to cut the dissipated power — accepting the\nadded noise and budgeting a small linear post-regulator for the sensitive analog\nrail. The thermal arithmetic, not the schematic, drove the choice.\n\n**A sensor reading buried in noise.** A precision sensor front end reads clean on\nthe prototype and noisy in production. The engineer scopes the input, finds the\nnoise is mains-frequency pickup, and traces it to a high-impedance node with a\nlarge loop area near a switching supply. The fix is to shorten and shield the\nloop, move the analog ground reference, and add a low-pass filter at the right\ncorner frequency — addressing source, path, and receptor in that order rather\nthan just cranking the gain and amplifying the noise too.","html":"<h2 id=\"scenarios\">Scenarios</h2>\n<p><strong>A board that fails EMC at the certification lab.</strong> A product passes every\nfunctional test and fails radiated emissions at a clock harmonic. The expert does\nnot reach for ferrites first. They open the layout, find the high-speed clock\ntrace routed over a split in the ground plane, and realize the return current was\nforced into a large loop that became an antenna. The fix is in the copper: route\nthe clock over solid ground, shorten the return loop, and slow the edge rate to\nthe slowest the timing allows. The filter would have masked a symptom; the layout\nfixed the cause.</p>\n<p><strong>A regulator that overheats in the enclosure.</strong> A linear regulator drops a high\ninput voltage to a low rail at significant current and runs fine on the open\nbench, then thermal-shuts-down inside the sealed product. The engineer computes\nthe dissipation (voltage drop times current) and the junction temperature through\nthe thermal-resistance chain, sees there&#39;s no path to ambient in the closed box,\nand switches to a switching regulator to cut the dissipated power — accepting the\nadded noise and budgeting a small linear post-regulator for the sensitive analog\nrail. The thermal arithmetic, not the schematic, drove the choice.</p>\n<p><strong>A sensor reading buried in noise.</strong> A precision sensor front end reads clean on\nthe prototype and noisy in production. The engineer scopes the input, finds the\nnoise is mains-frequency pickup, and traces it to a high-impedance node with a\nlarge loop area near a switching supply. The fix is to shorten and shield the\nloop, move the analog ground reference, and add a low-pass filter at the right\ncorner frequency — addressing source, path, and receptor in that order rather\nthan just cranking the gain and amplifying the noise too.</p>\n","wordCount":297},{"heading":"Related Occupations","id":"related-occupations","markdown":"Electrical engineers share the mechanical engineer's package and thermal budget\nin any electronic product and hand off heat and enclosure constraints both ways.\nEmbedded systems engineers write the firmware that runs the silicon and live at\nthe hardware/software boundary. Robotics engineers combine power electronics,\nsensing, and control. Network engineers build on the physical layer the EE\ndefines. Electricians install and maintain the power systems at building scale\nthat power engineers design. Mechanical engineers cooperate on every\nelectromechanical product.","html":"<h2 id=\"related-occupations\">Related Occupations</h2>\n<p>Electrical engineers share the mechanical engineer&#39;s package and thermal budget\nin any electronic product and hand off heat and enclosure constraints both ways.\nEmbedded systems engineers write the firmware that runs the silicon and live at\nthe hardware/software boundary. Robotics engineers combine power electronics,\nsensing, and control. Network engineers build on the physical layer the EE\ndefines. Electricians install and maintain the power systems at building scale\nthat power engineers design. Mechanical engineers cooperate on every\nelectromechanical product.</p>\n","wordCount":79},{"heading":"References","id":"references","markdown":"- *The Art of Electronics* — Horowitz & Hill\n- *High Speed Digital Design* — Howard Johnson & Martin Graham\n- *Noise Reduction Techniques in Electronic Systems* — Henry Ott\n- IPC-2221 — Generic Standard on Printed Board Design\n- IEC 61010 / FCC Part 15 — safety and emissions standards","html":"<h2 id=\"references\">References</h2>\n<ul>\n<li><em>The Art of Electronics</em> — Horowitz &amp; Hill</li>\n<li><em>High Speed Digital Design</em> — Howard Johnson &amp; Martin Graham</li>\n<li><em>Noise Reduction Techniques in Electronic Systems</em> — Henry Ott</li>\n<li>IPC-2221 — Generic Standard on Printed Board Design</li>\n<li>IEC 61010 / FCC Part 15 — safety and emissions standards</li>\n</ul>\n","wordCount":39}],"computed":{"wordCount":2272,"readingTimeMinutes":10,"completeness":1,"backlinks":["aerospace-engineer","biomedical-engineer","computer-hardware-engineer","electrician","embedded-systems-engineer","lineworker","marine-engineer","mechanical-engineer","network-engineer","nuclear-engineer","physicist","power-plant-operator","quantum-engineer","robotics-engineer","solar-installer","sound-engineer"],"verified":false,"aiDrafted":true,"unverifiedAiDraft":true},"git":{"created":"2026-06-26","updated":"2026-06-26","revisions":1,"authors":[{"name":"soul-atlas","commits":1}],"timeline":[{"date":"2026-06-26","author":"soul-atlas"}]},"citation":{"apa":"soul-atlas (2026). Electrical Engineer [SOUL]. SOUL Atlas. https://soul-atlas.github.io/occupations/electrical-engineer","bibtex":"@misc{soulatlas-electrical-engineer,\n  title        = {Electrical Engineer},\n  author       = {soul-atlas},\n  year         = {2026},\n  howpublished = {SOUL Atlas},\n  note         = {SOUL.md, version 2026-06-26},\n  url          = {https://soul-atlas.github.io/occupations/electrical-engineer}\n}","text":"soul-atlas. \"Electrical Engineer.\" SOUL Atlas, 2026. https://soul-atlas.github.io/occupations/electrical-engineer."}}